Traditional semiconductors and IC devices are typically packaged in a variety of ways to provide redistribution from the terminals on the die to a spacing that is conducive to cost effective printed circuit board (“PCB”) fabrication techniques. In many cases, the size and distance between die terminals is so small that the device cannot be connected to the final PCB without some sort of fan out or routing. The packages also serve to protect the fragile silicon or provide additional functions such as thermal management or near device decoupling. In many cases, the size and distance between die terminals is so small that the IC device cannot be connected to the final PCB without some sort of re-routing interface.
Most IC devices are produced with terminals in either a peripheral pattern that runs along the edges of the device or an area array pattern that spans across the surface of the device. A main method for attachment when the terminals are in an area array pattern is to connect the terminals with solder. Basically, the package has a field of terminals that correspond to the IC device terminals. Solder is applied to one or both of the terminals and reflowed to create the mechanical and electrical connection in a process commonly called flip chip attachment, since the IC device is flipped over to mate the terminals on the die to the terminals on the IC package substrate.
The IC devices in these types of packages are often under-filled with an epoxy of some type to provide support and strength to the joints so they remain connected during use and do not break due to thermal expansion mis-match or shock. In both cases, the connection of the device to the package is generally not reworkable once packaged and if there is a missing or broken connection it is difficult to repair.
There also has been advancements in recent years in both package types where multiple devices are placed in the same package, creating what has been nicknamed SiP or system-in-package. Once the IC devices are packaged, the IC devices are usually tested in a variety of ways to determine the reliability and performance of the devices in the package as they would be used in the final application. In many cases, the functional performance of the device is not known prior to placing it into the package and if the packaged device fails testing the cost of the package and processing is lost.
Area array packaging has been utilized for many years, and provides a method for interconnecting devices with larger terminal counts than peripheral lead packaging. In general, the area array packaging is more expensive due to the larger pin counts and more sophisticated substrates required. The main limitations for area array packaging are the terminal pitch, thermal management, cost, ability to rework faulty devices and reliability of the solder joint.
As IC devices advance to next generation architectures traditional area array packages have reached mechanical and electrical limitations that require alternate methods. For example, increased terminal count, reduction in the distance between the contacts known as terminal pitch, and signal integrity have been the main drivers that impact area array package design. As terminal counts go up, the area array package essentially gets larger due to the additional space needed for the terminals. As the package grows larger, costs go up and the relative flatness of the package and corresponding PCB require compliance between the contact members in the area array package and the terminal pad to accommodate the topography differences and maintain reliable connection.